The present invention relates generally to asynchronous circuits. More particularly, this invention involves a plurality of cascaded asynchronous cells forming a queue for high speed transfer of data completely independent of timing or clock sources.
Since the introduction of the present day computer and data processing system, considerable development has been made towards providing faster computing devices. Increases in speed of overall operation have heretofore come primarily from increases in the speed of operation of the relative parts and components of the data processing system or computer. However, asynchronous circuits and systems have been the subject of considerable investigation in recent years due to both the increase in speed of operation which can be achieved and other properties of such circuits. Asynchronous circuits are distinguished from synchronous circuits in that the latter operates on a distinct time cycle wherein transfer of each particular bit of information is restricted to a preselected and well-defined time period or clock cycle. In contrast, data transfer in an asynchronous system is not dependent upon a timing or clock source. One such asynchronous system is disclosed in U.S. Pat. No. 3,757,231 Faustini. The form of storage used in his cell and the separation of the shift control logic from the data storage, however, have their drawbacks. For example, the use of separate control logic requires more gates and results in a slower transfer rate.
Other asynchronous systems have been disclosed in the literature. However, each system has its own peculiar mode of data representation, transfer, and storage. In general, these other systems have differed in function from the present invention and/or have not provided optimum speed for data transfer.